Various exemplary embodiments relate to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device having pillars for defining an isolation trench and a method for forming an isolation trench between the pillars of a vertical channel transistor.
As semiconductor devices can be highly integrated, the cell dimensions integrated on an associated wafer can be decreased. Since this decrease in dimension can lead to a decrease in the channel length of a planar-type transistor, a shorting effect such as a Drain Induced Barrier Lowering (DIBL), a hot carrier effect or a punch through effect can occur. Therefore, with a planar-type transistor structure, there exists a limitation on improving the integration degree of the semiconductor devices.
To overcome the above integration limitation of the planar-type transistor, researchers have introduced a vertical channel transistor structure designed to increase the integration degree while securing the channel length of the transistor.
FIG. 1A is a plan view describing a typical semiconductor device including a vertical channel transistor.
Referring to FIG. 1A, the vertical channel transistor includes a plurality of pillar patterns P vertically protruding from a substrate 100. The pillar patterns P are arranged having a width parallel to the upper surface of the substrate 100 and extending perpendicular from the upper surface of the substrate 100. Herein, the substrate 100, at a portion centered between the pillar patterns P includes an isolation trench T isolating an impurity region for a bit line. A word line WL is formed to electrically connect a surrounding gate electrode (not shown), which surrounds the lower sidewalls of pillar patterns P above the substrate 100 and extending parallel to the upper surface of the substrate 100.
FIGS. 1B to 1D display cross-sectional views of the semiconductor device of FIG. 1A taken along the second direction B-B′. The figs. describe a method for fabricating a typical semiconductor device which includes a vertical channel transistor.
Referring to FIG. 1B, island-type first hard mask patterns 110 are formed above the substrate 100. The pillar patterns are formed by using first hard mask patterns 110 as barriers and then etching the substrate 100 to a certain depth. Herein, the first hard mask patterns 110 preferably include a nitride layer 110A in a lower portion and an oxide layer 110B in an upper portion. In the lower portion 110A of the first hard mask patterns 110, a pad oxide layer 120 can be formed.
A gate insulation layer 130 is formed encapsulating the resultant pillar patterns P and over the substrate. A surrounding gate electrode 140 is formed on lower sidewalls of pillar patterns P surrounding the gate insulation layer 130. Nitride layer spacers 150 are formed encapsulating the resultant gate insulation layer 130 and the surrounding gate electrode 140.
An impurity region (not shown) for a bit line is then formed by implanting impurity ions into the substrate 100 between the pillar patterns P. An insulation layer 160, including an oxide layer, is formed surrounding the pillar patterns P.
Second hard mask patterns 170 are formed above the resultant structure. Line-type photoresist patterns 180 are formed above the second hard mask patterns 170 covering the pillar patterns P and exposing a region for an isolation trench T. However, limitations in the fabrication process may cause a miss match between the photoresist patterns 180 and the region for the isolation trench T.
Referring to FIG. 1C, the second hard mask patterns 170 and the insulation layer 160 are etched by using the photoresist patterns 180 as an etch barrier, thereby exposing the substrate 100 in the isolation trench region between the pillar patterns P.
Herein, when the photoresist patterns 180 and the region for the isolation trench T are mismatched with each other by lack of an overlay margin, the nitride spacers 150 formed on the sidewalls of the pillar patterns P can be damaged. In this case, the surrounding gate electrode 140 and the pillar patterns P may also be exposed and damaged.
While the nitride spacers 150 on the sidewalls of one pillar pattern P are damaged, the insulation layer 160 overlay remains on the sidewalls of the other pillar pattern P. Thus, a plurality of the isolation trenches T over the substrate 100 may be formed having irregular widths W.
Referring to FIG. 1D, the exposed substrate 100 is selectively etched to a certain depth Dt. Thus, the isolation trench T extending in the first direction is formed in the substrate 100 between the pillar patterns P. Furthermore, low etch selectivity of the nitride spacers 150 to the substrate 100 may cause further damage to the nitride spacers 150. Accordingly, since the nitride spacers 150 cannot function as an etch barrier during a subsequent damascene word line formation process, the surrounding gate electrode 140 may become more exposed, resulting in damage.
As semiconductor devices become more highly integrated, limitations caused by the lack of the overlay margin are getting harder to overcome. Thus, the integration of semiconductor devices reaches the limits during a typical semiconductor device formation process.
The above limitations in the semiconductor device fabrication process do not only occur in cases including bar-type pillar patterns P where the upper and lower widths are the same, but also in cases with the pillar patterns having recessed lower widths.